This application claims the priority of Korean Patent Application No. 2004-37656, filed on May 27, 2004, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.
1. Field of the Invention
The present invention relates to a nonvolatile memory device and a method of manufacturing the same, and more particularly, to a memory device such as an Electrically Erasable Programmable Read Only Memory (hereinafter, referred to as “EEPROM”) device, and a method of manufacturing the same.
2. Description of the Related Art
As known in the art, unlike a dynamic random access memory and a static random access memory, a nonvolatile memory device refers to a device in which data is not erased even when the power supply is not connected. In an EEPROM device of the nonvolatile memory device, a higher voltage is applied to its gate to perform programming and erasure operations. In more detail, the programming and the erasure of the EEPROM device are performed by an F-N tunneling wherein electrons tunnel through a tunnel oxide film formed in a portion of a channel region. The EEPROM device is disclosed in “IEEE Standard Definitions and Characterization of Floating Gate Semiconductor Arrays (IEEE std 1005-1998).”
The EEPROM device can perform the erasure in one byte unit, that is, in an eight-bit unit. The EEPROM device includes a selection transistor at each of the bytes to erase each of the bytes.
FIG. 1 is a circuit diagram schematically illustrating a general EEPROM device for performing the erasure operation at each of the bytes.
As shown in FIG. 1, a unit cell of the EEPROM device includes a memory cell block 10 comprised of one byte (eight unit-bits), and a selection transistor 20 to select the memory cell block 10.
The memory cell block 10 is comprised of eight unit-bits as described above, and the unit bit is comprised of a high voltage transistor (HV) for switching a signal of bit lines BL1-BL8 when a word line WL is selected, and a memory transistor (MT) to operate when the selection transistor 20 is switched. At this time, the memory transistor (MT) substantially refers to the EEPROM device, and includes a tunneling oxide film, a floating gate electrode and a control gate electrode.
The selection transistor 20 transmits a signal from the control line (C/L) to the memory transistor (MT) when the word line (WL) is selected. At this time, it is important that the selection transistor 20 is designed to have almost 0V of a threshold voltage and a body effect to transmit a majority of voltage of the control line (C/L) to the memory transistor (MT) without a voltage drop. In a conventional art, the selection transistor 20 is formed in a bare semiconductor substrate, for example, in a P-type semiconductor substrate to have almost 0V of the threshold voltage and the body effect.
It is also required that the EEPROM device be formed in a narrower area due to the high integration of the semiconductor device. Accordingly, a conventional method of reducing an area of the memory cell block 10 to reduce the area of the EEPROM device has been proposed. In other words, in the conventional EEPROM device, the memory cell block 10 occupies an area of about 40 to 120 μm2, and the selection transistor 20 occupies an area of about 10 to 15 μm2, which is very small in comparison with the memory cell block 10. Therefore, efforts have been exacted to reduce the area of the memory cell block 10 occupying most of the EEPROM device.
Currently, due to the remarkable development of a photolithography process, a unit bit of the memory cell block 10 can be reduced up to 1.0 to 3.0 μm2 in area, and the memory cell block 10 can be also reduced up to 10 to 25 μm2 in area.
If the memory cell block 10 is reduced in area, the selection transistor 20 occupies an area that is never negligible in the EEPROM device. It is required that the selection transistor 20 be reduced in area to manufacture a highly integrated EEPROM device.
A conventional method of reducing the channel length of the selection transistor 20 has been proposed to reduce the area of the selection transistor 20.
However, if the channel length of the selection transistor 20 is reduced during a state when gate and drain voltages (word line voltage and control line voltage) are applied, a high electric field is formed in the channel region, thereby reducing the threshold voltage of the selection transistor 20, and generating a leakage current in a junction region.
Due to the reduction of the threshold voltage and the generation of the leakage current in the selection transistor 20, the selection transistor 20 is turned on in an unwanted state undesirably. Accordingly, the memory transistor (MT) can be erroneously operated.